High-speed latches and flip-flops are useful in many applications (e.g., data sampling, clock deskew, etc.) in the electrical arts and are often an essential part of design of digital circuits. Various different structures and architectures have been proposed for high-speed latch and flip-flop designs, including static, dynamic, single phase, multiphase, clocked complementary metal-oxide-semiconductor (CMOS), transmission gate, and many others. Increasingly, circuit designers are employing current mode logic (CML) latches in their designs due to their superior performance at very high frequencies and other advantages as compared to other latch architectures.
An example of a traditional CML latch 100, as known in the art, is depicted in FIG. 1. A current mode logic latch typically comprises a sample stage 102, a hold stage 104, and a current source 106. Sample stage 102 may comprise transistors 108a, 108b, and 110, and drain resistors 112a and 112b. Each drain resistor 112a, 112b may be coupled between the drain terminal of a corresponding transistor 108a, 108b, respectively, and a high potential voltage source (e.g., VDD). Each transistor 108a, 108b may in turn be coupled at its gate terminal to a differential input (e.g., Vin+ or Vin−) and at its source terminal to the drain terminal of transistor 110. Transistor 110 may be coupled at its gate terminal to a periodic clock signal CLK and coupled at its source terminal to current source 106.
Hold stage 104 may comprise transistors 114a, 114b, and 116. Each of transistors 114a, 114b may be coupled at its drain terminal to the drain terminal of a corresponding transistor 108a, 108b, respectively, and at its source terminal to the drain terminal of transistor 116. In addition, transistors 114a and 114b may be cross-coupled such that the gate terminal of transistor 114a is coupled to the drain terminal of transistor 114b, and vice versa.
In operation, sample stage transistors 108a, 108b form a differential transistor pair to sense and track the input data represented by an input voltage Vin, and cross-coupled hold stage transistors 114a, 114b form a differential transistor pair to store the sensed data. These differential pairs are switched by the complementary signals of the periodic clock signal CLK and CLK′. When CLK is of a high voltage potential (and CLK′ is accordingly of a low voltage potential), substantially all of the current sourced by current source 106 passes through sample stage 102. On the other hand, when CLK is of a low voltage potential (and CLK′ is accordingly of a high voltage potential), substantially all of the current sourced by current source passes through hold stage 104. Thus, the periodic clock signal CLK periodically enables and disables each of sample stage 102 and hold stage 104 in a complementary fashion (e.g., sample stage 102 is enabled while hold stage 104 is disabled, and vice versa).
The differential pair of sample stage 102 functions as a CML inverter, driven by complementary data signals. When Vin is of a high voltage potential, substantially all of the current sourced by current source 106 passes through resistor 112a and transistor 108a and as a result, the voltage at the drain terminal of transistor 108a may obtain a low voltage potential (e.g., VDD−RDIss, where RD is the resistance of each of resistors 112a and 112b). At the same time, substantially no current passes through transistor 108b, and as a result, the voltage at the drain terminal of transistor 108b may obtain a high voltage potential (e.g., VDD). Accordingly, CML latch 100 produces a differential output signal Vout equal to the difference between the voltage potential at the drain terminal of transistor 108b (e.g., the node labeled “y” in FIG. 1) and voltage potential at the drain terminal of transistor 108a (e.g., the node labeled “x” in FIG. 1). The differential cross-coupled transistor pair of hold stage 104 forms a regenerative positive feedback structure which maintains Vout during the time in which hold stage 104 is enabled by the complementary clock signal CLK′. FIG. 5 depicts example waveforms for Vin, CLK, and Vout illustrating functionality of a CML latch.
Despite the advantages of conventional CML latches, in many technologies (e.g., submicron CMOS technologies), conventional CMOS latches may present voltage headroom problems. As an example, consider a submicron technology in which a typical power supply voltage VDD is 1.0V. Not uncommonly, a power supply may have 5% to 10% tolerance variations. Therefore, with a 1.0V VDD, the worst case power supply may be 0.9V. In the circuit of FIG. 1, the output voltage swing is set exclusively by the amount of tail current (ISS) and the value of the resistor load (RD) and is generally much smaller than VDD, in the order of a few hundred millivolts. Consider further that the CML latch is to be used in an application in which a single-ended-peak output swing of 0.2V is required. With a single-ended-peak output swing of 0.2V, the output common mode voltage of the latch circuit is 0.7V (e.g., VDD−0.2V). The conventional CML latch 100 may suffers from severe voltage headroom problems when designed in a 1.0V (worst case 0.9V) supply voltage. When CLK is of a high voltage potential, the common-mode voltage at the inputs (e.g., Vin+ and Vin−) has to be sufficiently high enough to ensure that transistors 108a, 108b, and 110 and a transistor (not shown) of current source 106 are operated in saturation mode. Similarly, when CLK′ is of a high voltage potential, the common-mode voltage at the outputs (e.g., Vout+ and Vout−) needs to drive transistors 114a, 114b, and 110 and a transistor (not shown) of current source 106 into saturation mode. Therefore, the common-mode voltage at both the inputs and the outputs need to satisfy the following relation:VDD−Swing>VCM>VTH-NMOS+2VDSAT-NMOS where VDD is the supply voltage, Swing is the output voltage swing, VCM is the common mode voltage; VTH-NMOS is the threshold voltage of an NMOS transistor (e.g., transistor 108a, 108b, 110, 114a, 114b, 116 or a transistor of current source 106), which may, by way of example, be about 0.4 to 0.5V in a submicron technology; and VDSAT-NMOS is the saturation drain-to-source voltage of the NMOS transistor which may, by way of example, be about around 0.2V in a submicron technology. As a result, a VCM larger than at least 0.8V (0.4V+2*0.2V) is required to operate the latch circuit properly. With a worst case VDD of 0.9V and a single-ended-peak output swing of 0.2V (and therefore an output common-mode voltage of 0.7V), the output common-mode voltage may be insufficient to drive the transistors into saturation mode. The design may therefore suffer from severe voltage headroom problems. The latch circuit cannot acquire a wide input common-mode range, and the output swing of the latch circuit is small reducing the robustness of the circuit. In addition, with the tail current source in the triode region, the power supply rejection (i.e., rejection of noise from the power supply) may be poor resulting in noisy output waveforms.
Addressing these problems in submicron CMOS technologies may be difficult because the threshold voltage VTH-NMOS and the saturation drain-to-source voltage VDSAT-NMOS often do not shrink proportionately with reductions in the power supply. Removing current source 106 as depicted in FIG. 2 is one possible method of addressing the headroom issue, thus relying on transistors 110 and 116 to provide a tail current. With this proposed solution, however, the tail current would be inaccurate due to at least the uncertainty of the common-mode voltage and the voltage swing of the CLK and CLK′ signals, which may results in an inaccurate output common-mode voltage as well as output swing. Also, with an inaccurate tail current, the transconductance of sample stage transistors 108a and 108b may vary significantly, requiring oversized transistors 108a and 108b for proper tracking operation. Another possible solution to address the headroom issue is to use low threshold voltage transistors. However, this requires extra mask steps in the manufacturing process that may not be available in a typical CMOS process. The extra mask steps to lower the threshold voltage also lay also render manufacturing costs prohibitively expensive.